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LoadSliceCore - Coggle Diagram

- - - - The data-part of the Store instructions
        are executed using the main queue
        
        This honors the load/store dependencies
  - - - IST (Instruction Slice Table)
        
        A cache without any data fields,
        just produces a hit/miss bit for addresses
      - RDT (Reg Dependence Table)
        
        A cache with lines for each register
        each line holds the address for the last instruction
        that has been written to it.
        
        Also caches the IST hit bits for the each address at each line